ONCLE (One Clock Ensemble) for Galileo’s Next-Generation Robust Timing System

Block diagram of the test bench for the CMCU+ EM high-level performance verification tests

CMCU+ EM (right) under testing with the test bench (left); (top-right: EM external controller PC; middle-right: EM box; bottom-right: Power supply and high-level command ON/OFF box)

ADEV of CMCU+ output (for AFS Set A on the left and AFS Set B on the right)

Test case: Medium-dynamic frequency jump on master PHM01 for AFS Set A

Test case: WFN level increase on master PHM01 for AFS Set A

Architecture of the proposed RCE for physical realization of GST for next-generation PTF

Simulation model of the PLL with PI filter algorithm

Phases of the master AHM1, the free-running AHM2, and the steered AHM2

Simulation model of the ONCLE algorithm with RCE output

Frequency stability in ADEV (including drift) for four individual AHM’s and RCE output (simulation results)

Simulation model of the CFDC algorithms

Correction of phase jump of 30 ps; y-axis represents phase difference [step] after phase comparator and the x-axis represents time in seconds (left: without correction; right: with correction)

Removal of failed clock with frequency jump of 8e-12 occurred at 25,000 s (left: frequencies of the failed clock and RCE without/with clock removal; right: zoom-in of frequency of RCE with clock removal)