Parameters of the Triple-Loop Architecture Implemented for Processing the BDS B1 Signals
| Parameter | Value |
|---|---|
| DLL order | 2 |
| DLL bandwidth | 2 Hz |
| Early-minus-late spacing BPSK(2) | 0.5 chips |
| Early-minus-late spacing BOC(1, 1) | 0.333 slots |
| BPSK(2) chip/BOC(1, 1) slot duration | 0.48876 μs |
| SPLL order | 2 |
| SPLL bandwidth | 2 Hz |
| PLL order | 3 |
| PLL bandwidth | 15 Hz |
| Initial integration time | 1 ms |
| Integration time after secondary code synchronization | 10 ms |